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SIMD Vectorisation (Simple Instruction Multiple Data)
Manager : Dimitri LECAS
Instructor : Dimitri LECAS
The concepts of vectorisation, which emerged in the 1970s, enabled the development of specialised machines adapted to numerical simulation, with exceptional performance for the time.
Although this category of computers subsequently disappeared, the concepts of vectorisation remain entirely relevant and, when they can be implemented, result in significant acceleration of code portions that lend themselves to it.
Hardware devices have therefore been introduced into "classic" scalar processors, notably through the AVX (Advanced Vector Extensions) added to the instruction sets of Intel and AMD's x86 architecture, and the SVE (Scalable Vector Extension) of ARM processors. Several variants have been progressively introduced into the architectures and their use is now essential to achieve good performance on current generations of processors.
Objectives
The objective of this training is to present the concepts of vectorisation and how to benefit from them on modern generations of processors:
- Introduction to SIMD (Simple Instruction Multiple Data) vectorisation
- Understanding the underlying concepts
- Implementing these concepts on concrete examples
- Target audience
- Prerequisites
- Duration and details
- Course content
- Course materials
- Upcoming sessions
Duration and details
This training lasts 1 day.
It takes place exclusively in-person at IDRIS premises in Orsay (91).
Attendance
Minimum: 8 people;
Maximum: 20 people.
Program
- Introduction
- What is SIMD?
- Benefits of SIMD
- Evolution of the technology
- Vectorisation issues
- Dependencies
- Function calls
- First Practical Session
- OpenMP SIMD
- The OpenMP SIMD standard
- Vector loop declaration with OpenMP SIMD
- Vector function declaration with OpenMP SIMD
- Second Practical Session
- Vectorisation gains
- Efficiency loss due to memory access
- Modeling vectorisation gains using the Roofline model
- Third Practical Session
- Tools
- Introduction to the INTEL Vector Advisor tool
- Introduction to the Maqao tool
- Fourth Practical Session
- Conclusion and Final Practical Session
💡 50% of the time will be dedicated to practical sessions
For efficient execution of the practical parts, they will take place on the Jean Zay supercomputer. A workstation with access to the IDRIS supercomputer is provided to learners. Experience in using a supercomputer, as well as prior access to it, are not required.
Course materials
All course materials, including slides, notes, and practical exercises, are provided under the following license: Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License (CC BY-NC-SA 4.0). For more details on the license, please consult this page.
To view the dates of the upcoming sessions for this training, visit the following page:
Registration
CNRS/French university staff | External participants |
Are you a CNRS or French university staff member? Your registration is free via our server. | Our training is aimed at all professionals from companies, public bodies and individuals. |